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1 isl54504, isl54505 +1.8v to +5.5v, 2.5 , single spst analog switches isl54504, isl54505 the intersil isl54504 and isl54505 devices are low on-resistance, low voltage, bidirectional, single pole/single throw (spst) analog switches designed to operate from a single +1.8v to +5.5v supply. targeted applications include battery powered equipment that benefit from low r on resistance (2.5 ), excellent r on flatness (0.6 ) , and fast switching speeds (t on = 25ns, t off = 15ns). the digital logic input is 1.8v cmos compatible when using a single +3v supply. cell phones, for example, often face asic functionality limitations. the number of analog input or gpio pins may be limited and digital geometries are not well suited to analog switch performance. this family of parts may be used to switch in additional functionality while reducing asic design risk. the isl54504 and isl54505 are offered in a 6 ld 1.2mmx1.0mmx0.4mm pitch tdfn package and a 6 ld sot-23 package, alleviating board space limitations. the isl54504 has one normally open (no) switch and isl54505 has one normally closed (nc) switch. features ? on-resistance (r on ) -v cc = +5.0v. . . . . . . . . . . . . . . . . . . . . 2.5 -v cc = +3.0v. . . . . . . . . . . . . . . . . . . . . 4.0 -v cc = +1.8v. . . . . . . . . . . . . . . . . . . . . 7.0 ?r on flatness (+4.5v supply) . . . . . . . . . . . . . 0.6 ? single supply operation . . . . . . . . +1.8v to +5.5v ? fast switching action (+4.5v supply) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . 6kv ? 1.8v cmos logic compatible (+3v supply) ? available in 6 ld tdfn and 6ld sot-23 packages ? pb-free available (rohs compliant) applications ? battery powered, handheld, and portable equipment - cellular/mobile phones -pagers - laptops, notebooks, palmtops ? portable test and measurement ?medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? table 1. features at a glance isl54504 isl54505 number of switches 11 sw no nc 1.8v r on 6 6 1.8v t on /t off 65ns/40ns 65ns/40ns 3v r on 4 4 3v t on /t off 30ns/20ns 30ns/20ns 5v r on 2.5 2.5 5v t on /t off 25ns/15ns 25ns/15ns package 6 ld tdfn, 6 ld sot-23 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. october 23, 2009 fn6552.2
2 fn6552.2 october 23, 2009 ordering information part number (notes 1, 4) part marking temp. range (c) package (tape and reel) (pb-free) pkg. dwg. # isl54504iruz-t (note 2) 4 -40 to +85 6 ld tdfn l6.1.2x1.0a ISL54504IHZ-T (note 3) 4504 -40 to +85 6 ld sot-23 mdp0038 isl54505iruz-t (note 2) 5 -40 to +85 6 ld tdfn l6.1.2x1.0a isl54505ihz-t (note 3) 4505 -40 to +85 6 ld sot-23 mdp0038 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 terminat ion finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free produc ts are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device in formation page for isl54504, isl54505 . for more information on msl please see techbrief tb363 . pin configurations (note 5) isl54504 (6 ld tdfn) top view isl54504 (6 ld sot-23) top view isl54505 (6 ld tdfn) top view isl54505 (6 ld sot-23) top view note: 5. switches shown for logic ?0? input. 3 2 1 6 5 4 in v+ gnd no n.c. com 4 5 6 1 2 3 n.c. in no gnd v+ com 3 2 1 6 5 4 in v+ gnd n.c. nc com 4 5 6 1 2 3 nc in n.c. gnd v+ com truth table logic isl54504 isl54505 0offon 1onoff note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions pin name function v+ system power supply input (+1.8v to +5.5v) gnd ground connection in digital control input com analog switch common pin no analog switch normally open pin nc analog switch normally closed pin n.c. no connect isl54504, isl54505
3 fn6552.2 october 23, 2009 absolute maximum ratings thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6.5v input voltages no, nc, in (note 4) . . . . . . . . . . . . -0.5v to ((v+) + 0.5v) output voltages com (note 4) . . . . . . . . . . . . . . . . -0.5v to ((v+) + 0.5v) continuous current no, nc, or com. . . . . . . . . . . . 300ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . 600ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . >6kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . >300v charged device model . . . . . . . . . . . . . . . . . . . . . >2.2kv thermal resistance (typical) ja (c/w) jc (c/w) 6 ld tdfn package (notes 7, 9). . 239.2 111.6 6 ld sot-23 package (note 8, 10) . 260 120 maximum junction temperature (plastic package). . +150c maximum storage temperature range. . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions v+ (positive dc supply voltage) . . . . . . . . . . . 1.8v to 5.5v analog signal range . . . . . . . . . . . . . . . . . . . . . . 0v to v+ v in (digital logic input voltage (in) . . . . . . . . . . . 0v to v+ temperature range . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. signals on nc, no, in, or com exceeding v+ or gnd are clamped by internal diodes . limit forward diode current to maximum current ratings. 7. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 8. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 9. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 10. for jc , the ?case temp? location is taken at the package top center. electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.0v, v inl = 0.8v (note 11), unless otherwise specified. boldface limits apply over the oper- ating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (note 15, see figure 4) 25 - 2.2 2.5 full - - 3 r on flatness, r flat(on) v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (notes 14, 15) 25 - 0.6 0.65 full - - 0.7 no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 0.3v, 5v, v no or v nc =5v, 0.3v 25 -25 1.5 25 na full -150 - 150 na com on leakage current, i com(on) v+ = 5.5v, v com = 0.3v, 5v, or v no or v nc = 0.3v, 5v, or floating 25 -30 2.8 30 na full -300 - 300 na dynamic characteristics tu rn-on tim e , t on v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1, note 15) 25 - 25 - ns full - 25 - ns turn-off time, t off v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1, note 15) 25 - 15 - ns full - 16 - ns break-before-make time delay, t d v+ = 5.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 3, note 15) full - 15 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 24 - pc off isolation r l = 50 , c l = 5pf, f = 1mhz, v com =1v p-p (see figure 3) 25 - 70 - db isl54504, isl54505
4 fn6552.2 october 23, 2009 total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l =32 25 - 0.15 - % total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 - 0.014 - % -3db bandwidth signal = 0dbm, r l = 50 25 - 250 - mhz no or nc off capacitance, c off v+ = 4.5v, f = 1mhz, v no or v nc =v com = 0v (see figure 5) 25 - 7 - pf com on capacitance, c com(on) v+ = 4.5v, f = 1mhz, v no or v nc =v com = 0v (see figure 5) 25 - 18 - pf power supply characteristics power supply range full 1.8 - 5.5 v positive supply current, i+ v+ = 5.5v, v in = 0v or v+ 25 - 0.028 0.1 a full - 1.1 2.5 a digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 2.4 -- v input current, i inh , i inl v+ = 5.5v, v in = 0v or v+ full -0.1 0.053 0.1 a electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 11), unless otherwise specified . boldface limits apply over the oper- ating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on tdfn v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (note 15, see figure 4) 25 - 3.3 3.5 full - - 4.5 on-resistance, r on sot-23 v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (note 15, see figure 4) 25 - 3.3 3.6 full - - 4.5 r on flatness, r flat(on) tdfn v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (notes 7, 15) 25 - 1 1.1 full - - 1.2 r on flatness, r flat(on) sot-23 v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (notes 7, 15) 25 - 1 1.2 full - - 1.3 dynamic characteristics tu rn- on ti me , t on v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1, note 15) 25 - 30 - ns full - 30 - ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1, note 15) 25 - 20 - ns full - 20 - ns charge injection, q v g = 0v, r g = 0 ,c l = 1.0nf (see figure 2) 25 - 16 - pc off isolation r l = 50 , c l = 5pf, f = 1mhz, v com =1v p-p (see figure 3) 25 - -70 - db to t a l h a r m o n i c distortion f = 20hz to 20khz, v com = 2v p-p , r l = 32 25 - 0.36 - % to t a l h a r m o n i c distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 - 0.03 - % electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.0v, v inl = 0.8v (note 11), unless otherwise specified. boldface limits apply over the oper- ating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units isl54504, isl54505
5 fn6552.2 october 23, 2009 -3db bandwidth signal = 0dbm, r l = 50 25 - 250 - mhz no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 6 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 15 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 18 - pf power supply characteristics positive supply current, i+ v+ = 3.6v, v in = 0v or v+ 25 - 0.013 - a full - 0.7 - a digital input characteristics input voltage low, v inl full - - 0.5 v input voltage high, v inh full 1.4 -- v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -0.1 0.058 0.1 a electrical specifications - 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v inh = 1v, v inl = 0.4v (note 11), unless otherwise specified. boldface limits apply over the operating tem- perature range, -40c to +85c. parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 1.8v, i com = 10ma, v no or v nc = 0v to v+ (note 15, see figure 4) 25 - 6 6.5 full - - 7 dynamic characteristics tu rn-on ti me , t on v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1, note 15) 25 - 65 - ns full - 95 - ns turn-off time, t off v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1, note 15) 25 - 40 - ns full - 65 - ns charge injection, q v g = v+/2, r g = 0 , c l = 1.0nf (see figure 2) 25 - 8.2 - pc digital input characteristics input voltage low, v inl full - - 0.4 v input voltage high, v inh full 1 -- v notes: 11. v in = input voltage to perform proper function. 12. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. parts are 100% tested at +25c. over-temperature limits established by characterization and are not production tested. 14. flatness is defined as the di fference between maximum and minimum value of on-resistance over the specified analog signal range. 15. limits establishe d by characterization and ar e not production tested. electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 11), unless otherwise specified . boldface limits apply over the oper- ating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units isl54504, isl54505
6 fn6552.2 october 23, 2009 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection figure 3. off isolation test circuit figure 4. r on test circuit 50% t r < 20ns t f < 20ns t off 90% v+ 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on () + ---------------------------- = switch input logic input v out r l c l com no or nc in 50 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v inh v inl c l v out r g v g gnd com no or nc v+ c logic input in analyzer r l signal generator v+ c 0v or v+ no or nc com in gnd v+ c v inl or v inh no or nc com in gnd v nx v 1 100ma r on = v 1 /i 1 * * i 1 = 10ma at v+ = 1.8v i 1 isl54504, isl54505
7 fn6552.2 october 23, 2009 detailed description the isl54504 and isl54505 are bidirectional, single pole/single throw (spst) an alog switches. they offer precise switching capability from a single 1.8v to 5.5v supply with low on-resistance (2.5 ) and high speed operation (t on = 25ns, t off = 15ns). the devices are especially well suited for portable battery powered equipment due to their low operating supply voltage (1.8v), low power cons umption (0.15w), low leakage currents (300na max) and tiny tdfn and sot-23 packages. the isl54504 is a single normally open (no) spst analog switch. the isl54505 is a single normally closed (nc) spst analog switch. external v+ series resistor for improved esd and latch-up immunity, intersil recommends adding a 100 resistor in series with the v+ power supply pin of the isl54504, isl54505 ic (see figure 6). during an overvoltage transient event (such as occurs during system level iec 61000 esd testing), substrate currents can be generated in the ic that can trigger parasitic scr structures to turn on, creating a low impedance path from the v+ power supply to ground. this will result in a significant amount of current flow in the ic, which can potentially create a latch-up state or permanently damage the ic. the external v+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. under normal operation the sub-microamp i dd current of the ic produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 7). to prevent forward biasing these diodes, v+ must be applied before any input sign als, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the v+ rail. logic inputs can easily be protected by adding a 1k resistor in series with the input (see figure 7). the resistor limits the input current below the threshold that produces permanent damage and the sub- figure 5. capacitance test circuit test circuits and waveforms (continued) v+ c gnd no or nc com in impedance analyzer v inl or v inh figure 6. v+ series resistor for enhanced esd and latch-up immunity in com 100 no nc v+ gnd c optional protection resistor isl54504, isl54505
8 fn6552.2 october 23, 2009 microamp input current produces an insignificant voltage drop during normal operation. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins (as shown in figure 7) will shunt the fault current to the supply or to ground, thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current. power-supply considerations the isl54504, isl54505 construction is typical of most single supply cmos analog switches in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 4v maximum supply voltage, the isl54504, isl54505 5.5v maximum supply voltage provides plenty of room for the 10% tolerance of 3.6v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.8v but the part will operate with a supply below 1.8v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the ?electrical specifications? tables starting on page 3 and the ? typical performance curves? starting on page 9 for details. v+ and gnd also power the internal logic and level shiftier. the level shiftier converts the input logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this family of switches cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. logic-level thresholds this switch family is 1.8v cmos compatible (0.5v and 1.4v) over a supply range of 2v to 3.6v (see figure 14). at 3.6v the v ih level is about 0.95v. this is still below the 1.8v cmos guaranteed high output minimum level of 1.4v, but noise margin is reduced. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 systems, the isl54504/isl54505 has a -3db bandwidth of 250mhz (see figure 15). the frequency response is very consistent over a wide v+ range and for varying analog signal levels. an off switch behaves like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to output. off isolation is the resistance of this signal feedthrough. figure 16 details the high off isolation provided by the isl54504, isl54505. at 1mhz, off isolation is about 70db in 50 systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off isolation due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog-signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. figure 7. overvoltage protection gnd v com v nx v+ in x optional protection resistor optional schottky diode optional schottky diode isl54504, isl54505
9 fn6552.2 october 23, 2009 typical performance curves t a = +25 c, unless otherwise specified. figure 8. on-resistance vs supply voltage vs switch voltage figure 9. on-resistance vs switch voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltage figure 12. turn-on time vs supply voltage f igure 13. turn-off time vs supply voltage r on ( ) v com (v) 01 234 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i com = 100ma v+ = 2.7v v+ = 3v v+ = 4.5v v+ = 5v r on ( ) v com (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v+ = 4.5v i com = 100ma +25c +85c -40c r on ( ) v com (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 v+ = 2.7v i com = 100ma +25c +85c -40c r on ( ) v com (v) 1 2 3 4 5 6 7 8 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v+ = 1.8v i com = 10ma +25c +85c -40c t on (ns) v+ (v) 0 10 20 30 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 +25c +85c -40c t off (ns) v+ (v) 0 10 20 30 40 50 60 70 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 +25c +85c -40c isl54504, isl54505
10 fn6552.2 october 23, 2009 die characteristics substrate potential (powered up): gnd transistor count: process: submicron cmos figure 14. digital switching point vs supply voltage figure 15. frequency response figure 16. off isolation figure 17. charge injection vs switch voltage typical performance curves t a = +25 c, unless otherwise specified. (continued) v+ (v) v inh and v inl (v) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v inh v inl frequency (hz) normalized gain (db) -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 100k 1m 10m 100m 1g v com = 1v p-p v+ = 1.8v to 5.5v frequency (hz) (db) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 1k 10k 100k 1m 10m 100m 1g v+ = 1.8v to 5.5v q (pc) v com (v) -20 -15 -10 -5 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v+ = 5v v+ = 3.3v v+ = 1.8v isl54504, isl54505
11 fn6552.2 october 23, 2009 isl54504, isl54505 ultra thin dual flat no-l ead plastic package (utdfn) b d a e 0.10 c 2x pin 1 top view 0.10 c 2x reference detail a 0.10 c 0.08 c 7x a3 a1 a c seating plane 5x l e 1 3 64 4x bottom view side view 0.10 cab 0.05 c b6x note 3 l1 detail a detail b pin 1 lead 0.1x45 chamfer detail b a3 a1 1.40 land pattern 1.00 0.30 0.35 0.20 0.45 0.40 0.20 10 l6.1.2x1.0a 6 lead ultra thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 0.95 1.00 1.05 - e 1.15 1.20 1.25 - e 0.40 bsc - l 0.30 0.35 0.40 - l1 0.40 0.45 0.50 - n 6 2 ne 3 3 0-12 4 rev. 2 8/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. ne refers to the number of terminals on e side. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.
12 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6552.2 october 23, 2009 for additional products, see www.intersil.com/product_tree isl54504, isl54505 sot-23 package family e1 n a d e 4 3 2 1 e1 0.15 d c 2x 0.20 c 2x e b 0.20 m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 0 +3 -0 gauge plane a mdp0038 sot-23 package family symbol millimeters tolerance sot23-5 sot23-6 a 1.45 1.45 max a1 0.10 0.10 0.05 a2 1.14 1.14 0.15 b 0.40 0.40 0.05 c 0.14 0.14 0.06 d 2.90 2.90 basic e 2.80 2.80 basic e1 1.60 1.60 basic e 0.95 0.95 basic e1 1.90 1.90 basic l 0.45 0.45 0.10 l1 0.60 0.60 reference n 5 6 reference rev. f 2/07 notes: 1. plastic or metal protrusions of 0.25mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. this dimension is measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. index area - pin #1 i.d. will be located within the indicated zone (sot23-6 only). 6. sot23-5 version has no center lead (shown as a dashed line).

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